A liquid crystal display device is often adopted as a display element in a television or a graphic display. There is a liquid crystal display device that includes a switching element such as a thin film transistor (hereinafter, referred to as a TFT) for each display pixel. In such a liquid crystal display device, even in a case where the number of display pixels is increased, no cross talk is generated between the display pixels neighboring each other. With this liquid crystal display device, it is possible to obtain an excellent display image. In this regard, the liquid crystal display device including the switching element for each display pixel is highly regarded particularly.
As shown in FIG. 24, such a liquid crystal display device mainly includes a liquid crystal display panel 500 and a driving circuit section. The liquid crystal display panel 500 includes a pair of electrode substrates with a liquid crystal composition being provided therebetween. On outer surfaces of the electrode substrates, polarization plates are attached, respectively.
A TFT array substrate, one of the pair of the electrode substrates, includes a plurality of data signal lines S(1) through S(N) and a plurality of scanning signal lines G(1) through G(M) on a transparent insulation substrate 100 made of a material such as a glass. The data signal lines and the scanning signal lines intersect each other and are provided in a matrix manner. On intersections of the data signal lines and the scanning signal lines, switching elements 102 are provided. A switching element 102 is made of a TFT connected to a pixel electrode 103. An alignment film is provided so as to cover these components on a substantially entire surface of the insulation substrate 100. Thus, the TFT array substrate is formed.
As in the case of the TFT array substrate, a counter substrate, which is the other one of the pair of the electrode substrates, includes a counter electrode 101 and an alignment film on an entire surface of a transparent insulation substrate made of a material such as a glass. The counter electrode 101 and the alignment film are laminated on the insulation substrate in this order. The driving circuit section includes a scanning signal line driving circuit 300 connected to each of the scanning signal lines of the liquid crystal panel thus formed, a data signal line driving circuit 200 connected to each of the data signal lines of the liquid crystal panel, and a counter electrode driving circuit COM connected to the counter electrode of the liquid crystal panel.
As shown in FIG. 25, the scanning signal line driving circuit 300 includes (i) a shift register section 300a that includes M numbers of flip flops connected to each other by a cascade connection and (ii) selection switches 300b switched in accordance with outputs from the flip flops.
A selection switch 300b has one input terminal VD1 and the other input terminal VD2. Via the input terminal VD1, a gate ON voltage (Vgh voltage) having a sufficient level to turn on the TFT is inputted, whereas via the input terminal VD2, a gate OFF voltage (Vgl voltage) having a sufficient level to turn off the TFT is inputted. A data signal (GSP) is sequentially transferred to each of the flip flops in accordance with a clock signal (GCK), and then sequentially outputted to each of the selection switches 300b. In response to this, the selection switches 300b selectively output the Vgh voltages, which turn on TFTs, to the scanning signal lines G(1) through G(M) for one scanning period (TH), and then output the Vgl voltages, which turn off the TFTs, to the scanning signal lines G(1) through G(M). As a result, video signals outputted from the data signal line driving circuit 200 to the data signal lines S(1) through S(N) are written into corresponding pixels, respectively.
Patent Document 1 discloses a scanning signal line driving circuit in which a VD1 voltage is generated in the following circuit. That is, the VD1 voltage is generated in a circuit that, as shown in FIG. 26, includes (i) a capacitor Ccnt and a resistor Rcnt for carrying out an electric charging and discharging, respectively, (ii) an inverter INV for controlling the electric charge and discharge, and (iii) switches SW1 and SW2 for switching between the electric charging and discharging. The switch SW1 includes one terminal via which a signal voltage Vdd is applied. The signal voltage Vdd is a direct voltage having a Vgh voltage at a sufficient level to turn on a TFT. The switch SW1 includes the other terminal which is connected to one end of the resistor Rcnt and that of the capacitor Ccnt. The other end of the resistor Rcnt is grounded via the switch SW2. The switch SW2 is opened and closed in accordance with an Stc signal inputted via the inverter INV. The Stc signal has the same cycle as one scanning period. Also, the switch SW1 is opened and closed in accordance with the Stc signal.
In a case where the Stc signal is at a high level, the switch SW1 is closed, whereas the switch SW2 receives an Stc signal of a low level via the inverter INV, and is opened in response to the Stc signal. In contrast, in a case where the Stc signal is at a low level, the switch SW1 is opened, whereas the switch SW2 receives an Stc signal of a high level via the inverter INV, and is closed in response to the Stc signal.
An output signal VD1 thus generated in the circuit is supplied via the input terminal VD1 of the scanning signal line driving circuit 300 shown in FIG. 25. As shown in FIG. 27, the Stc signal is a timing signal for controlling a gate decay period. The Stc signal has the same cycle as the one scanning period (TH).
While the Stc signal is being at the high level, the switch SW1 is closed, whereas the switch SW2 is opened. As a result, the output signal VD1, which has the same voltage level as the Vgh voltage, is supplied via the input terminal VD1 of the scanning signal line driving circuit 300. In contrast, while the Stc signal is being at the low level, the switch SW1 is opened, whereas the switch SW2 is closed. As such, an electric charge acquired in the capacitor Ccnt is discharged via the resistor Rcnt, thereby gradually decreasing the voltage level. As a result, a waveform of an output signal VD1a appears to be saw-tooth as shown in FIG. 27.
If the output signal VD1 generated in the circuit is supplied via the input terminal VD1 of the scanning signal line driving circuit 300, it is possible to readily obtain a waveform in which a decay (a decay of a gate OFF voltage outputted to each of the scanning signal lines) on the scanning signal lines has a slope (see VG(j) in FIG. 27). By arranging the gate OFF voltage outputted to each of the scanning signal lines so that its waveform has slopes in a saw-tooth manner, as described above, it is possible to control the slope, depending on a signal retarded transfer property of the scanning signal lines. Thus, it is possible to make a level shift to be generated in a pixel electric potential substantially equally on a display plane, the level shift being generated by a parasitic capacitance collaterally associated with the scanning signal lines.
(Patent Document 1)    Japanese Unexamined Patent Application Publication, Tokukai, No. 2003-345317 (published on Dec. 3, 2003)
(Patent Document 2)    Japanese Unexamined Patent Application Publication, Tokukai-hei, No. 6-3647 (published on Jan. 14, 1994)